finally, EUV in Europe https://ec.europa.eu/commission/presscorner/detail/en/ip_26_329

PDKs are free-of-charge but proprietary... I guess patents make these things too hard, and free access is already a massive thing, but I still feel awkward

*the PDKs were apparently originally released a few months before the factory line itself, but seems to be operational now

overall, having access to 2nm and 14Å right away is extremely positive

oh hey, there's IGZO DRAM, seems like they're betting on it for 3D stacking

gosh wish I could apply for imec internship

second tier politicians holding plastic representations of transistors in bunnysuits is truly peak professional clownery https://www.imec-int.com/en/press/imec-inaugurates-nanoic-pilot-line-accelerating-innovation-sub-2nm-systems-chip

(is it wrong if I want one of those tho)

so yeah, overall, imec's NanoIC looks: pretty solid

there's a few more experimental lines in the works tho, one of which makes general purpose chips:

- FAMES, a consortium hosted by the French Alternative Energies and Atomic Energy Commission (CEA), providing 7nm FD-SOI (a cheaper, non-EUV planar process tech)

the rest are:

- APECS, a Fraunhofer ISIT project providing packaging and integration
- WBG, hosted by the National Research Council of Italy (CNR) as part of the Chips JU consortium, focused on SiC and GaN manufacturing for power and RF (process node is unknown and budget was the lowest, so likely not too fancy)
- PIXEurope, yet another consortium led by the Catalan government's ICFO, working on photonic chips (no public details seem to be out yet)

Relevant links:

https://www.nanoic-project.eu/
https://fames-pilot-line.eu/
https://www.apecs.eu/
https://www.wbg-pilot-line.eu/
https://pixeurope.eu/
https://topictree.ideal-ist.eu/topic/3532
https://topictree.ideal-ist.eu/topic/3533
https://topictree.ideal-ist.eu/topic/3534
https://topictree.ideal-ist.eu/topic/3535
https://topictree.ideal-ist.eu/topic/5776

....wow I just learned a lot about how EU research works

can I say btw, I might be MORE hyped about FAMES that NanoIC

it promises to be open as well, it has a budget close to that of NanoIC, yet it's built using cheaper, way more reproducible tech, with a process node that lets you build something equivalent to a Zen 2/3 chip

think about that

remember, 7nm was supposedlly impossible without EUV, 14nm were deemed the last process node with DUV

yet here we are, China bruteforcing its way into 3nm while the EU is aiming at 7nm with a very, VERY scalable DUV pipeline

oh, FAMES is kinda cheating too and they're doing double patterning (SADP)

truly SAD....p

https://www.sciencedirect.com/science/article/pii/S0038110125002096

and yeah, it is 193nm immersion DUV

this could be done just like SMIC did (FinFET + 193nm immersion DUV + SADP)

SMIC is also doing 5nm FinFET and 3nm GAAFET with 76nm immersion DUV + SAQP (quad patterning)

but I guess FD-SOI (with good old planar SOI MOSFETs (aka SOIFET)) is still easier and cheaper, as well as more efficient

heya I am: a very normal cat of girl with very normal brainworms

and in case you wonder: "what about bulk CMOS?" yeah not happening

> In conventional transistors, the channel region below the gate is depleted of mobile charge, leaving the dopant atoms ionized,” he said. “The charge from those atoms, along with the gate work function, sets the threshold voltage. The depth of the depletion region controls the electrostatics. Below the depletion region is neutral silicon, with a lot of mobile carriers

https://semiengineering.com/22nm-process-war-begins/

https://semiengineering.com/bulk-cmos-versus-fd-soi/

so THAT is where the "FD" comes from: fully depleted

fascinating

looking at the design of the gates does actually give an intuitive idea of why one is cheaper than the other

https://www.researching.cn/ArticlePdf/m00098/2021/42/2/023102.pdf

(omega gates are also called OSGFET, but honestly we should just call them ΩFET because it's cool and gay and sell them at ΩMart)

making everything planar does seem to suggest that the gates are way harder to break, thus

1) easier to manufacture without failure, but also
2) more reliable and longer-lasting

hmmmmmmmmmmmmmm

yeah I don't know, I just like SOIFET stuffs, they seem like the logical way to go

@xerz o o o omega mart

@kadse YOU HAVE NO IDEA WHAT'S IN STORE FOR YOUUUUUUUUUUUUUUUUUUUUUU

also uh,

reading those articles above, I've realized that TSMC and everyone else were doing multiple patterning all along, because 20nm without it was deemed impossible

still seems to be double patterning tho

FD-SOI at 22nm is definitely single patterning... Samsung and STMicro *have* 18nm FD-SOI made on DUV, no idea if single or multi-patterned, but I'd assume the latter since they'd have probably bragged about it otherwise?

oh hey

the comparison between the cost of patterning on FD-SOI (193i SADP) and FinFET/GAAFET (EUVESADP) was on the Wikipedia all along

https://en.wikipedia.org/wiki/Multiple_patterning#Patterning_costs

so uh

yeah, the math makes a TON of sense now

even with the advances that Imec is doing with EUV, you'd still rather do quad patterning with DUV

thus, FD-SOI will always be cheaper, even if solely because of patterning

consider the following: 7nm FD-SOI RISC-V processors with CHERI

you attach an ePaper, OLED or MicroLED screen (there's already watches with it, just you wait) and pretty much any modern battery (whenever semi-solid SiC, regular Li-Ion or even Na-Ion, not assuming Donut has a real product just yet)

and you got a dirt cheap computer that could last for weeks on battery power at performance good enough to compile Rust on

the best part about all of this is that, yeah, we've already peaked

we've already developed and are in the process of deploying almost all of the tech that's feasible and we could dream of, AND that tech makes everything we could possibly want perfectly viable

we don't need to wait to find out what something better will be like

we can just design it

today

tech is: so gay aaaaaaaaaaaaaaAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

(please also refer to: https://owo.cafe/@xerz/116103167105556204 )

@xerz cheri

...oh gosh, there's also NC-FDSOI (shouldn't it be NC-FD-SOI... or NC-FD-SOI-MOSFET or something...?)

https://www.mdpi.com/2079-4991/14/10/837

oh gosh oh god this keeps getting worse

https://www.sciencedirect.com/science/article/pii/S0038110125000127

(btw, can I mention that a ton of chip research seems to be done at Granada??????)

btw, funny to see people saying "28nm is the last real node oh wait 22nm is the last real node"

https://www.monolithic3d.com/blog/28-nm-the-last-node-of-moores-law
https://sst.semiconductor-digest.com/2014/03/moores-law-has-stopped-at-28nm/
https://www.edn.com/28nm-was-last-node-of-moores-law/
https://semiwiki.com/semiconductor-manufacturers/intel/6703-shootout-at-22nm/

you fools

it was 45nm

why does this website go so hard https://www.newport.com/n/deep-uv-photolithography

> Agentic EDA

die

btw, the hard-going website says this about DUV

> Quadruple patterning has provided a solution for patterning features as small as 5 nm.

hmmmmmmmmmmmmmmmmm