current mood: what if we made a functional CPU where registers are treated as immutable arguments/return values, and where instead of using interrupts for e.g. timers, we just provide their values as registers?

....wait, weren't call stacks and stack architectures supposed to address that in a way

gosh tho, I'm: really realizing now how blurry the lines between "CPU", "kernel" and "virtual machine" are

they're really all just implementing computers of their own, because "computers" are really about behavior and interface

just, some of them by composition, others by complete replacement of the world underneath

and so you can basically implement everything from one into the other if you're smart enough (whenever it makes sense is a different matter) (still: want tho )

alsoalso: the base RISC-V architecture does indeed do something along the lines of what I'm describing

https://docs.riscv.org/reference/isa/unpriv/zicsr.html

https://docs.riscv.org/reference/isa/unpriv/counters.html#7-1-1-zicntr-extension-for-base-counters-and-timers

there's still interrupts, but they're supposed to be for unrecoverable situations

https://docs.riscv.org/reference/isa/priv/rnmi.html

gosh I love how nerdy this architecture is

I'm 👌 this close to writing a RISC-V book for learning to code from scratch like the 80s assembly/BASIC ones

since CSRs aren't standardized tho, I guess I'd write it specifically for a QEMU implementation or for an ESP32?

@xerz i don’t get hardware at all but i know that there’s at least 10 different things currently running on my laptop that can be considered its own computer so yeah

@xerz tired: C is a system language
wired: java is a system language
inspired: JavaScript and python and everything else are all system languages

@xerz python is a system language if you find the right robotics chip

@twinkle yeah, there's MicroPython of course

some will dismiss that as "not machine language, so just another program on top of the Real Machine™"

to which I say:

begone

https://www.jopdesign.com/

https://www.cpushack.com/2016/05/21/azul-systems-vega-3-54-cups-of-coffee/

https://en.wikipedia.org/wiki/Jazelle

guess who just went and read through the documentation of the ESP32, including Chinese-only specs without translating, to conclude "oh yeah, that'd be quite easy" https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-lcdkit/user_guide.html

I'm seeing *free* ESP32-C3s on AliExpress

this might not be the worst of ideas

@xerz do it

@ulveon I

might?????

I wanted to learn how to make controllers for rhythm games anyway, this could be a gateway into that as well

@xerz whats a cpu regester?

@cutesobri You know how programs have variables? welp, the CPU saves them inside "registers", which are basically tiny (S)RAM within the CPU cores with fancy names like "EAX" (on x86) or "a0" (RISC-V)

they do this because going from the CPU to the RAM takes the microscopic equivalent of days (registers work in <1ns, superfast, while RAM takes microseconds or even milliseconds)

@xerz oh thats cool so its tiny hyper quick bits of ram in the cpu

@cutesobri ye

@xerz if it's immutable, how could it be a timer if time moves? Like if we treat this tiny bit of ram like a immutable value answer pair, how could we use that as a timer? How do timers actually work?

@cutesobri the idea is, the timer itself changes, but you can't touch that variable/register

you're just not responsible for time moving forward, so the system itself remains pure as much as it can... after all, so long as time is not a free (aka "non-local") variable, your program will always be predictable

been reading up on the specs for the thingie

and ngl this is surprisingly exciting?????????

like

like this is basically a faster PS1, even down to the CPU microarchitecture (although with 1 pipeline stage less, but yeah, both are in-order, scalar pipelined RISCs)... you can even do audio with PWM *and* I2S

the problem, however, is that there's no direct way to get a video signal out as far as I can tell

a bit of a tangent: just wondered why OpenSPARC and OpenPOWER failed where RISC-V didn't

as far as I can tell, OpenSPARC's specs were copyrighted, developed solely by Sun, didn't provide any patent rights, the T1 and T2 cores were server-only and GPLv2-licensed, and then it was all bought up by Oracle, so: yeah

https://www.robbuckley.co.uk/clippings/LinuxUser/OpenSPARC.pdf
https://www.oracle.com/a/tech/docs/systems/t2-06-opensparct2-core-microarch.pdf

but then OpenPOWER is supposed to be fine, right?

https://openpower.foundation/blog/final-draft-of-the-power-isa-eula-released/

ah okay, you still had to comply with an EULA that didn't want you to make changes, Java vibes but from IBM

and then you compare the archs, and

yeah, RISC-V feels strongly inspired by those preceding it, almost feels like a mix of MIPS and PowerPC

https://riscv.org/about/genealogy/

so it's such a weird turn of events that some Serbian guy had to come and create his own arch

wow

such google

many generosity

very credits

https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf

hmmmmmmmmmmmmmm

is this what I think it is

https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/api-reference/peripherals/i2s.html#_CPPv422i2s_pdm_tx_line_mode_t

ngl would be great if there were two I2S ports

there's still one at least

hmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm

https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/api-reference/peripherals/sdm.html

I wonder if I could basically take this and output multiple channels which I could split into audio and video

> Different ESP chip series might have different numbers of SDM channels. Please refer to Chapter GPIO and IOMUX in ESP32-C3 Technical Reference Manual for more details. The driver does not forbid you from applying for more channels, but it will return an error when all available hardware resources are used up. Please always check the return value when doing resource allocation (e.g., sdm_new_channel()).

one of the most fascinating footnotes of all time

> Four out of the 125 peripheral outputs (output index: 55 ~ 58 in Table 5.11-1) support 1-bit second-order sigma delta modulation. By default output is enabled for these four channels. This modulator can also output PDM (pulse density modulation) signal with configurable duty cycle.

ohmygosh we may have something here

so yeah, if I understand correctly, you can choose whatever GPIO pin you want to act as a lossy 8-bit DAC, up to 4 of them

I just wonder if it will be possible to output at a big enough voltage and sample rate for both audio and video

seemingly no one really knows this is a thing?????? I've only seen it mentioned for the S3, not the C3 https://www.atomic14.com/2024/01/05/esp32-s3-no-pins

this little smol is insane https://github.com/espressif/esp-idf/tree/v6.0/examples/system/freertos/basic_freertos_smp_usage

oh hey this board looks similar https://docs.zephyrproject.org/latest/boards/espressif/esp32c3_devkitc/doc/index.html

@xerz looks like the one that cost 4.XX euros.

@xerz Tianhe-2 if i remember, used processors based on the T2 or T2+ cores.

@xerz https://en.wikipedia.org/wiki/FeiTeng#Galaxy_FT-1500

@echedellelr correct lesbian

@xerz @echedellelr wow, both of you are very knowledgeable about hardware

@ArtistSynth @xerz xerz knows more

@echedellelr @ArtistSynth I have like 0 experience

@xerz @echedellelr to both of you: I can build a pc but youare beyond that

@ArtistSynth @echedellelr

what

how does that comparison even make sense

https://powercommons.org/about/why-openpower.html

for context, PowerCommons is a project trying to implement an FPGA soft processor based on the PowerPC IBM A2O

and all they have to say against RISC-V is "there's proprietary implementations :("

even tho there's way more open RISC-V cores than there's been POWER cores at all in the same timespan

> 502 Bad Gateway

lmao https://git.openpower.foundation/cores/a2o

I will concede something that people seem to be getting one detail wrong about OpenPOWER: no, hypervisors don't have to be proprietary

LPAR+PowerVM are a thing, suresure

but you also can do LPAR+KVM, without having to go through PowerVM

you just need to implement the "Logical Partitioning (LPAR)" part of the ISA specs

this isn't a supernew thing either, although perhaps it happened before RISC-V started making noise? https://www.talospace.com/2018/11/making-your-talos-ii-into-ibm-pseries.html

just noticed that RVA23 requires implementing Zkt (for constant-time execution, aka safety against timing attacks) and GOSH I love how well thought out this keeps looking like

this is so @echedellelr coded https://hackaday.com/2026/04/02/ask-hackaday-how-much-compute-is-enough/

btw, been talking a little bit with @nyx_lyb3ra about PowerPC and while it isn't more popular in the first place

spoilers: https://lowendmac.com/2024/keepin-the-03-dp-2-0-power-mac-g5-cool-what-worked-for-me/

yeah, so what happened was

https://512pixels.net/2022/11/the-sad-saga-of-the-500-mhz-power-mac-g4/
https://en.wikipedia.org/wiki/Power_Mac_G4

Motorola was late on releasing the G4, and it turned out to have terrible yields, so Apple released it with 50 MHz less on each config... yeahhhhhhhh

....and then the G5 happened

@xerz and I'm kinda reflected on that article. the only thing that makes me go like "I need a new cpu" was... audio

@ArtistSynth and yet I keep finding ways where my I wish my computer was faster (compiling, it's always compiling)

so, the G5 happened

Steve Jobs announced a partnership with IBM for the G5, they'd get to 3GHz and easily blow Intel's Pentium 4 out of the park, solid plan

but the initial Power Mac G5 was: a monolith

https://www.theregister.com/2004/01/22/ibm_claims_massive_power_cut/

don't worry, IBM has it under control, just need to go to 90nm

. . .

. . . . .

https://512pixels.net/2025/06/3ghz-power-mac-g5-broken-promise/

yeah

Apple gave up by June 2004. This, added to IBM itself dropping OS/2 and its entire PC division at the same time, essentially killed PowerPC.

https://www.macworld.com/article/171607/ibm-16.html

Sure, they got the consoles on board. The Wii's Gekko and the Xbox 360's Xenon were made on the long promised 90nm process node, while the PS3 waited just a few months longer in exchange of the bleeding-edge 65nm.

That didn't help for long tho, because game dev, like almost everything else from thereon, was happening on x86. Particularly as the rest of competitors (read: Itanium) died off.

@xerz https://github.com/OpenPOWERFoundation/a2o that is the original source, also the website loads for me.

@xerz you did not know talos II?

it was superfamous here in fedi in that time, the problem is that was rich-prized.

@xerz in muylinux there is a spanish user who is or was an owner of a Talos II

@echedellelr the Github is a mirror of the link I shared, goodgood to see it's back online at least... someone's still working on OpenPOWER, I guess

@echedellelr of course I knew about it, it's more about the specifics of whenever KVM could work natively or required PowerVM

reading this Reddit comment and

yeah, I can agree, RISC-V is something special if solely because of how it's already pretty much finished before hardware has even started shipping

@xerz the post underappreciates a bit that Ubuntu 24.04 already ships for RISC-V, before that ISA update even.

@echedellelr I think the post is just saying "look at how bleeding edge and well-supported RISC-V is before hardware has even shipped", so I get why 24.04 wasn't mentioned

but yeah, could have made it clearer 26.04 isn't the first LTS release since... welp, I didn't know that either

@xerz "more advanced on risc-v than x86" lmao
newer x86_64 profiles break compatibility with older hardware for very little benefit, because most software that can actually take advantage of newer extensions already does using hardware feature detection and graceful fallback to older instruction sets

meanwhile riscv isn't common in serious production workloads so they keep bumping the requirements because hardware that's only a couple years old ranges from not great to worthless so very few people will actually care

an argument can be made about software ecosystem maturity relative to the state of the hardware, but it's all largely academic until that catches up (never)

@novenary welp, performance improvements are definitely measurable when compiling for x86_64-v2 or better, you can check with e.g. CachyOS or AlmaLinux

that said, yeah, the impact is nowhere near as large as it should be because of the workarounds

and honestly, RVA23 hardware is starting to ship in the coming weeks, so it's not exactly "never"... I just wonder how much of a market it has, since

it will already be compatible with almost everything FOSS out of the box,

but it will not be substantially more competitive unless it's priced accordingly and shipping in volume

@novenary like imho the launch of RVA23 (and thus RISC-V for personal computers/phones as a whole) entirely depends now on making and fulfilling promises like e.g. "90% of the performance at 50% the price"

the fact that this is feasible, and that software compatibility is not a huge issue, is just a massive achievement

but it needs to happen

@xerz this thread is starting to get big enough to lag tuba :<